1. Field of the Invention
The present invention relates to a multilayer wiring board for mounting thereon an electronic element such as a semiconductor chip having connection electrodes arranged in the form of a lattice or a semiconductor device having connection terminals arranged in the form of an area array.
2. Description of the Related Art
FIG. 1 is a cross-sectional view of a circuit board 5 having a semiconductor chip 4 mounted thereon by flip-chip bonding. The semiconductor chip 4 has an electrode carrying surface having a peripheral zone in which electrode terminals 6 are arranged in two rows and each thereof is electrically connected to one of wiring patterns 7 on the circuit board 5.
FIG. 2 is a plan view of the circuit board 5 having lands 8 provided thereon and the wiring patterns 7 connected to the lands 8. The lands 8 are arranged in positions corresponding to that of the electrode terminals 6 of the semiconductor chip 4 and each of the lands 8 is connected to one of the wiring patterns 7.
In the shown arrangement, the lands 8 are arranged in two rows in the same manner as the electrode terminals 6 and the lands 8 of the outer row have wiring patterns 7 extending outward directly therefrom and the lands 8 of the inner row have wiring patterns 7 extending outward therefrom through spaces between the lands 8 of the outer row. In the arrangement shown in FIG. 2, the number of the lands 8 is not large and the wiring patterns 7 can extend outward in one layer through spaces between the outer lands 8 from all of the inner lands 8 without difficulty.
However, when the number of the electrode terminals 6 of the semiconductor chip 4 is large, the wiring patters 7 cannot extend outward in one layer from all of the inner lands 8, depending on the land pitch and the number of lands.
The circuit board 5 mounts the semiconductor chip 4 thereon by electrically connecting the electrode terminals 6 of the semiconductor chip 4 to external connection terminals of the circuit board 5 via the wiring patterns 7. As shown in FIG. 3, when the number of the electrode terminals 6 is extremely large, wiring patterns 7 are formed in a plurality of layers to enable all electrode terminals 6 of a semiconductor chip 4 to be electrically connected to external connection terminals 9 of a circuit board 5. The symbol xe2x80x9c7axe2x80x9d denotes inner wiring patterns and the symbols xe2x80x9c5axe2x80x9d to xe2x80x9c5dxe2x80x9d denote wiring layers which constitute a multilayer wiring board 5.
When the number of electrode terminals 6 of a semiconductor chip 4 is not much large, a multilayer wiring board 5 only includes several wiring layers. However, when electrode terminals 6 are arranged in a much larger lattice such as 30xc3x9730 pins or 40xc3x9740 pins and at a reduced pitch of electrode terminals, a multilayer wiring board must include wiring layers in an increased number such as six to ten.
A multilayer wiring board for mounting a semiconductor device is produced by build-up method or other methods which enable wiring patterns to be formed in an increased density. However, the method of forming wiring patterns at high density to form multiple layers has problems in product yield, product reliability, and production cost. Specifically, a multilayer wiring structure is produced by a process including layer-by-layer forming wiring patterns and vias electrically connecting wiring patterns of adjoining layers, which process requires high precision and does not provide good reliability. Moreover, as the number of wiring layers is increased, it becomes more difficult to to ensure that all wiring layers contain no defects.
Therefore, the number of wiring layers of a multilayer wiring board should advantageously be reduced to ensure good product yield, product reliability and production cost.
The present invention is directed to a multilayer wiring board for mounting electronic elements such as a semiconductor chip having electrode terminals in a large number such as 40xc3x9740 pins or a semiconductor device having a mounting surface on which a large number of connection terminals are arranged to form an area array.
The object of the present invention is to provide a multilayer wiring board for mounting a semiconductor chip or a semiconductor device, in which the number of wiring layers is minimized to provide improved product yield, product reliability and production cost.
To achieve the object according to the present invention, there is provided a multilayer wiring board having a plurality of wiring layers, in which each of said wiring layers includes lands arranged in the form of a square lattice and wiring patterns each having one end connected to one of said lands and the other end extending outward beyond an outermost row of said lattice, said lands having a land pitch p and a land diameter d and said wiring patterns having a pattern width w and an interpattern space s, said p, d, w and s satisfying the following relationship:
pxe2x88x92d less than 2s+w
and
({square root over ( )}2)pxe2x88x92dxe2x89xa72s+w,
wherein said lattice has periodic land-free or vacant lattice sites, all lands in said outermost row have wiring patterns extending outward therefrom, and said land-free or vacant lattice sites provide a space through which wiring patterns extend outward from, and are connected to, lands of an inner row.
The present invention provides a multilayer wiring board having an improved arrangement of wiring patterns in each wiring layer to enable the number of wiring layers to be reduced.
The multilayer wiring board of the present invention may be produced by any of existing processes for producing a multilayer wiring board such as build-up method, etc.
Electronic elements such as a semiconductor chip or a semiconductor device have electrode terminals or connection terminals, which are usually arranged in the form of a square lattice. In order to reduce the number of wiring layers of a multilayer wiring board, the arrangement of wiring patterns in a wiring layer must be designed to provide efficient outward extension of wiring patterns from the lattice of electrode terminals or connection terminals with a minimized number of wiring layers.
Because wiring patterns usually extend outward through a space between adjacent lands, the arrangement of wiring patterns is generally designed in accordance with given conditions of a land pitch, a land diameter, a pattern width, and an interpattern space.
The multilayer wiring structure of the present invention is applied to the wiring pattern arrangement in which the land pitch p, the land diameter d, the pattern width w and the interpattern space s have a relationship therebetween which satisfies the following formula 1) and 2):
Pxe2x88x92d less than 2s+w,xe2x80x83xe2x80x831)
and
({square root over ( )}2)pxe2x88x92dxe2x89xa72s+w.xe2x80x83xe2x80x832)
The present invention provides the most efficient outward extension of wiring patterns from lands under this condition. FIG. 4 shows the definition of the land pitch p, the land diameter d, the pattern width w and the interpattern space s. The land pitch p refers to the distance between centers of adjacent lands and the interpattern space s refers to a required minimum distance between adjacent wiring patterns.
The formula 1) and 2) define a condition in which electrode terminals of a semiconductor chip or connection terminals of a semiconductor device or other electronic elements are very close to each other so that even one wiring pattern cannot pass through a space between adjacent lands which form a side of a square lattice unit with the four corners each occupied by one land while at least one wiring pattern can pass through a space defined by the diagonal segment of the square lattice unit.
In a multilayer wiring board, when a land in a first wiring layer has a wiring pattern extending outward therefrom, a land in the corresponding position in the adjoining second wiring layer need not have a wiring pattern extending outward therefrom, and therefore, outward extension of wiring pattern may only be considered for the other lands in the second wiring layer that have no corresponding lands having wiring patterns extending outward therefrom in the first wiring layer. This means that designing of the wiring pattern must include consideration as to how wiring patterns can extend outward in the second wiring layer in accordance with the outward extension of wiring patterns in the first wiring layer.
The outward extension of wiring pattern is designed on the following basic rule.
In a row of n continuous lands from a square lattice arrangement of lands, when nxe2x88x922 intermediate lands are removed from the row to form a space between two lands at both ends of the row, m wiring patterns can pass the space, in which the number m is given by the integer part of:
(p(nxe2x88x921)xe2x88x92dxe2x88x92s)/(w+s),
where
p: land pitch,
d: land diameter,
w: pattern width, and
s: interpattern space.
In the present invention, the wiring pattern is designed on this rule and under the limitation defined by the formula 1) and 2).
In the square lattice arrangement of lands under the limitations 1) and 2), no wiring pattern can pass through the space between two adjacent lands. Therefore, if the conventional outward extension design were applied to this lattice, the outward extension would have to be effected for lands of the outermost row alone for each wiring layer. In the lattice forming an nxc3x97n matrix of lands, about n/2 wiring layers would be required. This number of wiring layers is about twice that required in a square lattice in which one wiring pattern can pass a space between two adjacent lands, so that no efficient outward extension can be achieved from the viewpoint of the practically acceptable production step number and production cost, particularly when the lattice size or the value n is very large.
To solve this conventional problem, the present invention provides a practically acceptable, efficient outward extension by using a square lattice of lands which includes at least the outermost row of lands having periodic land-free or vacant lattice sites at an interval.
The land-free or vacant lattice sites are disposed to enable outward extension from lands of inner rows as well as lands of the outermost row. The land-free lattice sites are advantageously positioned to provide the substantially the same efficiency in the outward extension of wiring patterns in a wiring layer as that obtained when one wiring pattern can pass through the space between two adjacent lands.
The land-free lattice sites may be provided not only in the outermost row but also in the inner rows and may be provided either in a row or rows in one direction at an interval or in two or more vertically intersecting rows at respective intervals.
In practice, the proportion of the number of land-free lattice sites to the total number of lattice sites can be about 10% or less to provide sufficient effect. The proportion can be further reduced when lands in the core portion of a lattice are used for power supply or ground and need not have wiring patterns outward extending therefrom.
The positions of land-free lattice sites may be determined on the above-mentioned rule for the number m to provide a highest efficiency. Specifically, the wiring pattern arrangement is designed by so determining the positions of land-free or vacant lattice sites as to provide the most efficient outward extension of wiring patterns based on the specific land pitch, land diameter, wiring pattern width and interpattern space.